boots your firmware and inference on N real targets. 0 setup, 0 hardware to own.
microcontroller, arm or risc-v box, gpu. cilicon sits in your ci, cross-builds for every chip you target, boots the artifact in a cloud emulator, and runs your inference where it ships, proving it actually works on the silicon before it does. every target in parallel, owning zero hardware. one pr check, boot-proven and signed.
# add cilicon to your CI, .github/workflows/cilicon.yml
- uses: neural-alloy/cilicon@v1
# or run it locally, nothing to install, builds AND boots in parallel
$ uvx --from git+https://github.com/neural-alloy/cilicon@v1 cilicon run
→ cilicon · 3 targets · fanned across cloud containers
✓ jetson/linux-arm64 · boots real arm64 kernel → your init
✓ stm32h7/cortex-m · boots virtual UART → 'BOOT OK'
✗ pi5/linux-arm64 · panic VFS: unable to mount root fs
2 / 3 passed · ~1m wall-clock · size budgets checked
--attestation signs each pass (ed25519 DSSE boot proof)
Supports hardware from
